LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 42

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.7 (06-29-10)
STRAP NAME
speed_strap_1
duplex_strap_1
BP_EN_strap_1
FD_FC_strap_1
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
Port 1 Speed Select Strap: Configures the default value
for the
the PHY_BASIC_CTRL_1 register (See
When configured low, 10 Mbps is selected. When
configured high, 100 Mbps is selected.
This strap also affects the default value of the following bits:
Refer to the respective register definition sections for
additional information.
Port 1 Duplex Select Strap: Configures the default value
for the
PHY_BASIC_CTRL_1 register (See
When configured low, half-duplex is selected. When
configured high, full-duplex is selected.
This strap also affects the default value of the following bits:
Refer to the respective register definition sections for
additional information.
Port 1 Backpressure Enable Strap: Configures the
default value for the
(BP_EN_1)
(MANUAL_FC_1). When configured low, backpressure is
disabled. When configured high, backpressure is enabled.
Port 1 Full-Duplex Flow Control Enable Strap:
Configures the default value of the
Transmit Flow Control Enable (TX_FC_1)
Duplex Receive Flow Control Enable (RX_FC_1)
Port 1 Manual Flow Control Register
which are used when manual full-duplex control is selected.
When configured low, full-duplex Pause packet detection
and generation are disabled. When configured high, full-
duplex Pause packet detection and generation are enabled.
PHY_SPEED_SEL_LSB bit of the
Control Register (PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the
Advertisement Register (PHY_AN_ADV_x)
MODE[2:0] bits of the
(PHY_SPECIAL_MODES_x)
PHY_DUPLEX bit of the
Register (PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex (bit 6) of the
Negotiation Advertisement Register (PHY_AN_ADV_x)
MODE[2:0] bits of the
(PHY_SPECIAL_MODES_x)
Speed Select LSB (PHY_SPEED_SEL_LSB)
Duplex Mode (PHY_DUPLEX)
bit of the
DATASHEET
Port x PHY Auto-Negotiation
Port 1 Backpressure Enable
Port 1 Manual Flow Control Register
Port x PHY Special Modes Register
Port x PHY Special Modes Register
42
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Port x PHY Basic Control
Port 1 Full-Duplex
Port x PHY Basic
Section
(MANUAL_FC_1),
bit in the
Port x PHY Auto-
Section
and
14.4.2.1).
Port 1 Full-
14.4.2.1).
bits in the
bit in
SMSC LAN9311/LAN9311i
PIN / DEFAULT
VALUE
1b
1b
1b
1b
Datasheet