LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 389
LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9311-NZW.pdf
(460 pages)
Specifications of LAN9311-NZW
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Standard
Quantity:
2
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.5.3.20
31:16
15:14
13:12
11:10
BITS
9:8
7:6
5:4
3:2
1:0
RESERVED
Priority 7 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 7.
Priority 6 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 6.
Priority 5 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 5.
Priority 4 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 4.
Priority 3 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 3.
Priority 2 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 2.
Priority 1 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 1.
Priority 0 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 0.
Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
This register specifies the Traffic Class table that maps the packet priority into the egress queues.
Register #:
1845h
DESCRIPTION
DATASHEET
389
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Revision 1.7 (06-29-10)
DEFAULT
11b
11b
10b
10b
01b
00b
00b
01b
-
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