LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 316

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.7 (06-29-10)
REGISTER #
1803h-1804h
1815h-183Fh
180Ah
180Bh
180Ch
180Dh
180Eh
1800h
1801h
1802h
1805h
1806h
1807h
1808h
1809h
180Fh
1810h
1812h
1813h
1814h
1840h
1841h
1842h
1843h
1844h
1845h
1846h
1811h
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
SWE_GLB_INGRESS_CFG
SWE_PORT_INGRESS_CFG
SWE_DIFFSERV_TBL_CMD
SWE_DIFFSERV_TBL_CMD_STS
SWE_ADMT_ONLY_VLAN
SWE_DIFFSERV_TBL_WR_DATA
SWE_DIFFSERV_TBL_RD_DATA
SWE_VLAN_WR_DATA
SWE_VLAN_CMD_STS
SWE_ALR_WR_DAT_0
SWE_ALR_WR_DAT_1
SWE_VLAN_RD_DATA
SWE_ALR_RD_DAT_0
SWE_ALR_RD_DAT_1
SWE_PORT_MIRROR
SWE_ALR_CMD_STS
SWE_PORT_STATE
SWE_PRI_TO_QUE
SWE_VLAN_CMD
SWE_ALR_CMD
SWE_ALR_CFG
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SYMBOL
Switch Engine CSRs
DATASHEET
Switch Engine ALR Command Register,
Switch Engine ALR Write Data 0 Register,
Switch Engine ALR Write Data 1 Register,
Reserved for Future Use
Switch Engine ALR Read Data 0 Register,
Switch Engine ALR Read Data 1 Register,
Reserved for Future Use
Switch Engine ALR Command Status Register,
Switch Engine ALR Configuration Register,
Reserved for Future Use
Switch Engine VLAN Command Register,
Switch Engine VLAN Write Data Register,
Reserved for Future Use
Switch Engine VLAN Read Data Register,
Reserved for Future Use
Switch Engine VLAN Command Status Register,
Section 14.5.3.11
Switch Engine DIFSERV Table Command Register,
Section 14.5.3.12
Switch Engine DIFFSERV Table Write Data Register,
Section 14.5.3.13
Switch Engine DIFFSERV Table Read Data Register,
Section 14.5.3.14
Switch Engine DIFFSERV Table Command Status Register,
Section 14.5.3.15
Reserved for Future Use
Switch Engine Global Ingress Configuration Register,
Section 14.5.3.16
Switch Engine Port Ingress Configuration Register,
Section 14.5.3.17
Switch Engine Admit Only VLAN Register,
Switch Engine Port State Register,
Reserved for Future Use
Switch Engine Priority to Queue Register,
Switch Engine Port Mirroring Register,
316
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
REGISTER NAME
Section 14.5.3.19
Section 14.5.3.21
Section 14.5.3.1
SMSC LAN9311/LAN9311i
Section 14.5.3.8
Section 14.5.3.20
Section 14.5.3.9
Section 14.5.3.10
Section 14.5.3.18
Section 14.5.3.2
Section 14.5.3.3
Section 14.5.3.4
Section 14.5.3.5
Section 14.5.3.7
Section 14.5.3.6
Datasheet