LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 259
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LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9311-NZW.pdf
(460 pages)
Specifications of LAN9311-NZW
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Standard
Quantity:
2
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Microchip Technology
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
Note 14.42 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 14.43 The default value of this field is the result of the Auto-Negotiation process if the
Note 14.44 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via
Note 14.45 The default value of this field is determined via the SQE_test_disable_strap_mii
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
N e g o t i a t i o n ( V P H Y _ A N )
(VPHY_BASIC_CTRL)
(VPHY_SPEED_SEL_LSB)
VPHY_BASIC_CTRL register. Refer to
page 96
the
(PMT_CTRL). The NASR designation is only applicable when the
of the
configuration strap. Refer to
additional information.
Reset Control Register (RESET_CTL)
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
for information on the Auto-Negotiation determination process of the Virtual PHY.
DATASHEET
is set. Otherwise, this field reflects the
and
259
b i t o f t h e
Section 4.2.4, "Configuration Straps," on page 40
Duplex Mode (VPHY_DUPLEX)
Section 7.3.1, "Virtual PHY Auto-Negotiation," on
V i r t u a l P H Y B a s i c C o n t r o l R e g i s t e r
or
Power Management Control Register
is set.
Reset (VPHY_RST)
Revision 1.7 (06-29-10)
Speed Select LSB
bit settings of the
Auto-
for
bit
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