LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 226

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.7 (06-29-10)
BITS
4:3
2:1
5
0
Lock Enable GPIO 8 (LOCK_GPIO_8)
This bit enables/disables the GPIO 8 lock. This lock prevents a 1588 capture
from overwriting the Clock value if the 1588_GPIO8 interrupt in the
Interrupt Status and Enable Register (1588_INT_STS_EN)
due to a previous capture.
0: Disables GPIO 8 Lock
1: Enables GPIO 8 Lock
GPIO 9 Clock Event Mode (GPIO_EVENT_9)
These bits determine the output on GPIO 9 when a clock target compare
event occurs.
00: 100ns pulse output
01: Toggle output
10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output
11: RESERVED
Note:
Note:
GPIO 8 Clock Event Mode (GPIO_EVENT_8)
These bits determine the output on GPIO 8 when a clock target compare
event occurs.
00: 100ns pulse output
01: Toggle output
10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output
11: RESERVED
Note:
Note:
Reload/Add (RELOAD_ADD)
This bit determines the course of action when a clock target compare event
occurs. When set, the
(1588_CLOCK_TARGET_HI)
(1588_CLOCK_TARGET_LO)
Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)
1588 Clock Target Reload/Add Low-DWORD Register
(1588_CLOCK_TARGET_RELOAD_LO)
occurs. When low, the Clock Target Low and High Registers are
incremented by the Clock Target Reload Low Register when a clock target
compare event occurs.
0: Reload upon a clock target compare event
1: Increment upon a clock target compare event
The 1588_GPIO_OE[9] bit in the
Configuration Register (GPIO_CFG)
GPIO output to be controlled by the 1588 block.
The polarity of the pulse or level is set by the
GPIO_EVENT_POL_9 bit in the
Register
GPIO buffer type.
The 1588_GPIO_OE[8] bit in the
Configuration Register (GPIO_CFG)
GPIO output to be controlled by the 1588 block.
The polarity of the pulse or level is set by the
GPIO_EVENT_POL_8 bit in the
Register
GPIO buffer type.
(GPIO_CFG). The GPIOBUF[9] bit still determines the
(GPIO_CFG). The GPIOBUF[8] bit still determines the
1588 Clock Target High-DWORD Register
and
DESCRIPTION
are loaded from the
1588 Clock Target Low-DWORD Register
DATASHEET
when a clock target compare event
General Purpose I/O Configuration
General Purpose I/O Configuration
General Purpose I/O
General Purpose I/O
226
must be set in order for the
must be set in order for the
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
1588 Clock Target
is already set
1588
and
TYPE
R/W
R/W
R/W
R/W
SMSC LAN9311/LAN9311i
DEFAULT
00b
00b
Datasheet
1b
0b