LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 51

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
5.2.1
5.2.2
The following sections detail each category of interrupts and their related registers. Refer to
Chapter 14, "Register Descriptions," on page 167
1588 Time Stamp Interrupts
Multiple 1588 Time Stamp interrupt sources are provided by the LAN9311/LAN9311i. The top-level
1588_EVNT (bit 29) of the
event occurred in the
The
status of all 1588 interrupt conditions. These include TX/RX 1588 clock capture indication on Ports
2,1,0, 1588 clock capture for GPIO[8:9] events, as well as 1588 timer interrupt indication.
In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt
event must be enabled in the
(1588_EVNT_EN) of the
enabled via bit 8 (IRQ_EN) of the
For additional details on the 1588 Time Stamp interrupts, refer to
on page
Switch Fabric Interrupts
Multiple Switch Fabric interrupt sources are provided by the LAN9311/LAN9311i in a three-tiered
register structure as shown in
Register (INT_STS)
Engine Interrupt Pending Register
In turn, the
Register (SWE_IMR)
(Buffer Manager, Switch Engine, and Port 2,1,0 MACs).
The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager,
Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-
modules. These low-level registers provide the following interrupt sources:
In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must
be configured:
For additional details on the Switch Fabric interrupts, refer to
on page
—Status B Pending
—Status A Pending
—Interrupt Pending
—No currently supported interrupt sources. These registers are reserved for future use.
Buffer Manager
Pending Register
Switch Engine
Pending Register
Port 2,1,0 MACs
Pending Register
The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask
register
Interrupt Mask Register (SWE_IMR)
Register (MAC_IMR_x)
The desired Switch Fabric sub-module interrupt event must be enabled in the
Interrupt Mask Register (SWE_IMR)
Bit 28 (SWITCH_INT_EN) of the
IRQ output must be enabled via bit 8 (IRQ_EN) of the
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
161.
81.
(Buffer Manager Interrupt Mask Register (BM_IMR)
Switch Engine Interrupt Pending Register (SWE_IPR)
(Switch Engine Interrupt Mask Register (SWE_IMR)
(Buffer Manager Interrupt Mask Register (BM_IMR)
provides indication that a Switch Fabric interrupt event occurred in the
(BM_IPR))
(SWE_IPR))
(MAC_IPR_x))
provide status and enabling/disabling of all Switch Fabric sub-modules interrupts
(Port x MAC Interrupt Mask Register (MAC_IMR_x)
1588 Interrupt Status and Enable Register
Interrupt Enable Register (INT_EN)
Interrupt Status Register (INT_STS)
for the Port 2,1,0 MACs)
1588 Interrupt Status and Enable Register
Figure
Interrupt Configuration Register
(SWE_IPR).
DATASHEET
Interrupt Enable Register (INT_EN)
5.1. The top-level SWITCH_INT (bit 28) of the
for the Switch Engine, and/or
51
for bit-level definitions of all interrupt registers.
Interrupt Configuration Register (IRQ_CFG)
provides indication that a 1588 interrupt
must be set, and IRQ output must be
Section 6.6, "Switch Fabric Interrupts,"
for the Buffer Manager,
Section 11.6, "IEEE 1588 Interrupts,"
(1588_INT_STS_EN).
(IRQ_CFG).
and
provides enabling/disabling and
Port x MAC Interrupt Mask
Switch Engine Interrupt Mask
and
and
must be set
(1588_INT_STS_EN), bit 29
and
Buffer Manager Interrupt
Switch Engine Interrupt
Port x MAC Interrupt
Revision 1.7 (06-29-10)
Switch Engine
Interrupt Status
Switch Engine
Switch