LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 237

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.6.5
27:20
BITS
31
30
29
28
CSR Busy (CSR_BUSY)
When a 1 is written to this bit, the read or write operation (as determined by
the R_nW bit) is performed to the specified Switch Fabric CSR in
Address
complete, at which time the bit will clear. In the case of a read, the clearing
of this bit indicates to the Host that valid data can be read from the
Fabric CSR Interface Data Register
SWITCH_CSR_CMD and SWITCH_CSR_DATA registers should not be
modified until this bit is cleared.
Read/Write (R_nW)
This bit determines whether a read or write operation is performed by the
Host to the specified Switch Engine CSR.
0: Write
1: Read
Auto Increment (AUTO_INC)
This bit enables/disables the auto increment feature.
When this bit is set, a write to the
(SWITCH_CSR_DATA)
(CSR_BUSY)
(CSR_ADDR[15:0])
When this bit is set, a read from the
Register (SWITCH_CSR_DATA)
Address (CSR_ADDR[15:0])
bit should be cleared by software before the last read from the
SWITCH_CSR_DATA register.
0: Disable Auto Increment
1: Enable Auto Increment
Note:
Auto Decrement (AUTO_DEC)
This bit enables/disables the auto decrement feature.
When this bit is set, a write to the
(SWITCH_CSR_DATA)
bit. Once the write command is finished, the
(CSR_ADDR[15:0])
When this bit is set, a read from the
Register (SWITCH_CSR_DATA)
Address (CSR_ADDR[15:0])
bit should be cleared by software before the last read from the
SWITCH_CSR_DATA register.
0: Disable Auto Decrement
1: Enable Auto Decrement
RESERVED
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
This read/write register is used in conjunction with the
(SWITCH_CSR_DATA)
Refer to
registers indirectly accessible via this register.
(CSR_ADDR[15:0]). This bit will remain set until the operation is
This bit has precedence over the
Offset:
Section 14.5, "Switch Fabric Control and Status Registers," on page 309
bit. Once the write command is finished, the
will automatically increment.
will automatically decrement.
register will automatically set the
will automatically set the
to control the read and write operations to the various Switch Fabric CSR’s.
and set the
and set the
1B0h
DESCRIPTION
Switch Fabric CSR Interface Data Register
will automatically increment the
Switch Fabric CSR Interface Data Register
will automatically decrement the
(SWITCH_CSR_DATA). The
Switch Fabric CSR Interface Data
Switch Fabric CSR Interface Data
DATASHEET
CSR Busy (CSR_BUSY)
CSR Busy (CSR_BUSY)
Auto Decrement (AUTO_DEC)
237
CSR Address
CSR Busy (CSR_BUSY)
Size:
CSR Busy
CSR Address
Switch Fabric CSR Interface Data Register
CSR
32 bits
CSR
CSR
bit. This
bit. This
Switch
bit
TYPE
R/W
R/W
R/W
R/W
RO
SC
Revision 1.7 (06-29-10)
for details on the
DEFAULT
0b
0b
0b
0b
-