L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 113

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Layer_2_Key_Table_3
Description: The fourth stage of a MAC address look-up is performed by this table.
Table 127. Layer_2_Key_Table_3 Register Parameters
Table 128. Layer_2_Key_Table_3 Field Parameters
This fourth stage of a MAC address look-up involves the use of 64 records, each containing three keys. The three
keys are compared against the search argument. The results of these comparisons serve to select one of the four
index values for use in the next stage of the look-up.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
layer_2_key_{0..2}[47:0]
12
16
20
0
4
8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
1
Field Name
2
3
4
5
6
7
Figure 94. Layer_2_Key_Table_3 Register Diagram
8
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
9
0x000c_3000
10
Value
2048
11
NA
Agere Systems - Proprietary
32
64
32
1
Spacing = 8.0
Instances = 3
Offset = 0.16
Mode = R/W
Parameters
12
13
layer_2_key_0[31:0]
layer_2_key_1[31:0]
layer_2_key_2[31:0]
14
15
16
17
A set of 48-bit MAC address values. These values
are compared against the search argument. The
results of these comparisons are used to select one
of four index values for use in the next stage of the
look-up.
18
19
20
21
layer_2_key_0[47:32]
layer_2_key_1[47:32]
layer_2_key_2[47:32]
22
23
8
Description
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
31
0
113