L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 43

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Functional Description
Supervisor Packet Transmission
The ET4148-50 supervisor processor performs packet transmissions by faking packet receptions.
The supervisor presents a packet to the ET4148-50’s receive packet processing as if it were a normal receive
packet. However, rather than using look-up results derived from the packet’s contents, the Layer 2 and ACL look-
up operations use look-up results that have been queued by the supervisor in advance of reception of the packet.
These faked look-up results are used to direct the packet to the queues associated with the transmit ports desired
by the supervisor.
Because of this requirement to preload the look-up results, the transmit packet data structure is headed by a series
of fields that hold such information as a transmit port map, priority level, and the like.
Two independent queues are available to the supervisor for packet transmission. The two queues have a strict pri-
ority relationship. Whenever the high-priority queue is not empty, it preempts the operations of the low-priority
queue.
Data Structures
The following three sets of information stored in the supervisor’s memory are necessary for packet transmission:
1. Packet transmission FIFO.
2. Packet descriptor blocks.
3. Packet segments.
Figure 20. Supervisor Packet Transmission Data Structures
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
TRANSMIT
Agere Systems - Proprietary
PACKET
FIFO
DESCRIPTOR
PACKET
BLOCK
SEGMENTS
PACKET
ET4148-50
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