L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 84
L-ET4148-50C-DB
Manufacturer Part Number
L-ET4148-50C-DB
Description
Manufacturer
LSI
Datasheet
1.L-ET4148-50C-DB.pdf
(298 pages)
Specifications of L-ET4148-50C-DB
Lead Free Status / RoHS Status
Supplier Unconfirmed
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16
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ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Acl_Ip_Key_Table_8
Description: This table performs the ninth and final stage of IP address look-up.
Table 70. Acl_Ip_Key_Table_8 Register Parameters
84
0
4
8
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
2
3
4
5
6
7
8
Figure 53. Acl_Ip_Key_Table_8 Register Diagram
(continued)
9
ip_src_addr_index_0[8:0]
ip_src_addr_index_1[8:0]
ip_src_addr_index_2[8:0]
0x0003_0000
10
16384
Value
256
11
NA
44
64
1
Agere Systems - Proprietary
12
13
ipv6_key_0[127:96]
ipv6_key_1[127:96]
ipv6_key_0[63:32]
ipv6_key_1[63:32]
ipv6_key_0[95:64]
ipv6_key_1[95:64]
ipv6_key_0[31:0]
ipv6_key_1[31:0]
14
15
16
17
18
19
20
21
ip_dest_addr_index_0[8:0]
ip_dest_addr_index_1[8:0]
ip_dest_addr_index_2[8:0]
22
23
8
24
7
Preliminary Data Sheet
25
6
26
5
27
Agere Systems Inc.
4
28
3
29
2
April 2006
30
1
31
0
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