L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 88

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Acl_Port_Ace_Map_Table
Description: This table converts ACE map index values derived from TCP port indexes into ACE maps.
Table 76. Acl_Port_Ace_Map_Table Register Parameters
Table 77. Acl_Port_Ace_Map_Table Field Parameters
This table is addressed by Acl_Port_Ace_Map_Index_Table.port_ace_map_index[7:0] and returns the
64-bit ACE map value for the associated TCP port. An ACE map is a vector that identifies all of the ACEs for which
the associated TCP port number range registers a match.
The following figure shows where this table fits in the ACL processing pipeline.
88
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
protocol_ace_map[63:0]
0
4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
4
5
6
Figure 57. Acl_Port_Ace_Map_Table Register Diagram
7
(continued)
8
9
Figure 58. ACL Processing Pipeline
0x0004_0000
10
Mode = R/W
Parameters
Offset = 0.0
11
Agere Systems - Proprietary
Value
ACL Index
2048
256
NA
1
8
8
12
protocol_ace_map[63:32]
protocol_ace_map[31:0]
13
14
15
ACE Map Index Table
Port Number Look-up
ACL Result Tables
ACE Map Table
16
Port Number
ACL Result
The ACE map value.
Encoder
17
18
ACE Map
ACE Index
19
20
21
22
Description
23
8
Preliminary Data Sheet
24
7
25
6
26
5
Agere Systems Inc.
27
4
28
3
April 2006
29
2
30
1
31
0