L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 38

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Functional Description
Supervisor Packet Reception
Eight of the ET4148-50’s 408 internal queues are dedicated to supervisor use. The normal bridging processes
result in certain packets being forwarded to these queues. Typically, each queue is dedicated to a single purpose
(e.g., source address learning) or a limited range of purposes.
The Layer 2 address tables may be configured to forward or copy any arbitrary MAC destination address to the
supervisor. Also, certain types of packets are generally forwarded or copied to the supervisor. These packet types
include those with unknown MAC source addresses, IGMP packets, ACL logged packets, and others. Generally,
each of the supervisor’s eight queues are dedicated to only a very limited number of traffic types.
The packet queuing and buffering space within the ET4148-50 is limited, and the supervisor’s ability to keep up
with certain types of traffic may be very unlikely. Hence, the ET4148-50 transfers packets from its internal buffers to
buffers created within the supervisor’s memory system across the ET4148-50’s PCI bus. The ET4148-50 does this
as a PCI initiator.
Figure 16 shows how eight transmit queues are dedicated to the supervisor. These eight particular transmit queues
(ports 50 through 57) are associated in a one-to-one relationship with eight receive FIFOs that are established in
the supervisor’s memory space.
38
RECEIVE FIFOS IN SUPERVISOR MEMORY
ET4148-50
PCI CONTROLLER
Figure 16. Supervisor Packet Reception Structures
(continued)
PCI
PACKET BUFFER
Agere Systems - Proprietary
4:1
4:1
WRR QUEUE
SCHEDULING
TRANSMIT QUEUES
Preliminary Data Sheet
Agere Systems Inc.
April 2006