L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 155

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Packet_Buffer_Allocated_Buffer_Count
Description: Provides a real-time indication of the number of allocated buffers.
Table 196. Packet_Buffer_Allocated_Count Register Parameters
Table 197. Packet_Buffer_Allocated_Buffer_Count Field Parameters
This register provides a real-time indication of the number of buffers that are allocated per port.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
allocated_buffer_count[13:0]
REFERENCE
0
PORT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
XG1
51
2
Parameter
Field Name
3
XG0
50
Figure 146. Packet_Buffer_Allocated_Buffer_Count Register Diagram
4
SU1
49
5
SU0
6
48
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
G47
47
8
Figure 147. Port Numbering Scheme
G46
46
9
PORT NUMBERING SCHEME (TABLE INDEXING)
Agere Systems - Proprietary
10
G45
45
11
G44
44
12
Instances = 1
Offset = 0.18
13
Mode = R/W
Parameters
14
15
0x000c_b900
16
Value
208
NA
52
G3
1
4
4
17
3
18
G2
The number of buffers allocated to the corre-
sponding port.
2
19
G1
1
20
allocated_buffer_count_{0..51}[13:0]
21
G0
0
22
23
8
Description
24
7
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
25
6
26
5
27
4
28
3
ET4148-50
29
2
30
1
31
155
0