L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 234

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Supervisor_Int_Mask_Clear
Description: Clears bits in Supervisor_Int_Mask.
Table 325. Supervisor_Int_Mask_Clear Register Parameters
Table 326. Supervisor_Int_Mask_Clear Field Parameters
Writing ones to bit locations in this register causes the corresponding bits in Supervisor_Int_Mask to be cleared.
For the definitions of the various mask clear bits, see Supervisor_Ind, page 228,
234
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
int_mask_clear[15:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
Field Name
1
2
3
4
Figure 247. Supervisor_Int_Mask_Clear Register Diagram
5
6
(continued)
7
8
9
Instances = 1
10
Offset = 0.16
0x000c_c460
Parameters
Mode = WO
Agere Systems - Proprietary
11
Value
NA
NA
4
1
4
1
12
13
14
15
16
Various interrupt mask clear bits.
17
18
19
20
21
22
Description
23
8
24
7
Preliminary Data Sheet
25
6
26
5
27
4
Agere Systems Inc.
28
3
29
2
April 2006
30
1
31
0