L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 242

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Supervisor_Rx_Fifo_Ptr
These pointers are used during the operation of the receive FIFOs. There are eight instances of the three-field
record diagrammed in Figure 254. The record at offset zero corresponds to receive FIFO zero.
As the ET4148-50 deposits packets into the FIFOs maintained within supervisor memory, it advances
rx_fifo_last_ptr[31:2]. At all times, this pointer identifies the last complete packet deposited into the super-
visor’s receive FIFOs. This pointer is set to point to the first 32-bit word of a receive packet data structure
(Supervisor_Rx_Packet.packet_start_ptr[31:2]). By interpreting this pointer, the supervisor is able to
know which packet is the last one in the FIFO and, hence, when it should cease processing receive packets for the
associated FIFO.
Whenever Supervisor_Rx_Fifo_Limits.rx_fifo_first_ptr[31:2] and rx_fifo_last_ptr[31:2]
are equal, the corresponding FIFO is empty.
There are eight records in this register. Each record corresponds to an individual supervisor receive queue accord-
ing to the following table.
Table 339. Supervisor Receive Queue and Corresponding Register Records
242
REFERENCE
QUEUE
Queue
400
401
402
403
404
405
406
407
SU7
407
SU6
406
(continued)
SU1
401
(continued)
SU0
400
Figure 255. Queue Numbering Scheme
399
QUEUE NUMBERING SCHEME
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
XG1
...
Agere Systems - Proprietary
392
Register Record
391
XG0
...
0
1
2
3
4
5
6
7
384
383
G47
...
376
15
G1
...
Preliminary Data Sheet
8
7
G0
...
Agere Systems Inc.
0
April 2006