PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 123

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
INCA-D
PSB 21473
Parallel Ports
9
Parallel Ports
The INCA-D features Port 0 (inculdes 8 bit P0H and 8 bit P0L), Port 1 (8 bit P1H and 8
bit P1L), Port 2 (14 bit), Port 3 (16 bit), Port 4 (6 bit), Port 6 (3 bit) and Port 7 (10 bit).
The I/O ports are true bidirectional ports and may be used for general purpose Input/
Output controlled via software or may be used implicitly by INCA-D’s integrated
peripherals or the External Bus Controller.
All port lines are bit addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers.
Internal pull transistors are connected to the ports if the corresponding bits of register
PxPUDEN are set to ’1’ . Either a pull down or a pull up transistors will be selected via
register PxPUDSEL.
The logic level of a pin is clocked into the input latch once per state time, regardless
whether the port is configured for input or output.
A write operation to a port pin configured as an input (DPx.y = ’0’) causes the value to
be written into the port output latch, while a read operation returns the latched state of
the pin itself. A read-modify-write operation reads the value of the pin, modifies it, and
writes it back to the output latch.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin
to have the written value, since the output buffer is enabled. Reading this pin returns the
value of the output latch. A read-modify-write operation reads the value of the output
latch, modifies it, and writes it back to the output latch, thus also modifying the level at
the pin.
General Remark for all register descriptions:
Unused register bits always have an undefined reset value. The reset value for a whole
register in hexadecimal notation does not apply to unused bits. Unused bits may be ’0’,
’1’, or ’-’. Only if indicated with ’-’ , a bit can be written as ’1’ or ’0’; in all other cases the
predefined value must be written.
Data Sheet
123
2003-03-31

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