PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 163

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

address windows (more than BUSCONs are available) on the expense of the overhead
for changing the registers and keeping appropriate tables.
Switching between predefined address windows automatically selects the bus mode
that is associated with the respective window. Predefined address windows allow to use
different bus modes without any overhead, but restrict their number to the number of
BUSCONs. However, as BUSCON0 controls all address areas, which are not covered
by the other BUSCONs, this allows to have gaps between these windows, which use the
bus mode of BUSCON0.
PORT1 will output the intra-segment address, when any of the BUSCON registers
selects a demultiplexed bus mode, even if the current bus cycle uses a multiplexed bus
mode. This allows to have an external address decoder connected to PORT1 only, while
using it for all kinds of bus cycles.
Note: Never change the configuration for an address area that currently supplies the
The usage of the BUSCON/ADDRSEL registers is controlled via the issued addresses.
When an access (code fetch or data) is initiated, the respective generated physical
address defines, if the access is made internally, uses one of the address windows
defined by ADDRSEL4...1, or uses the default configuration in BUSCON0. After
initializing the active registers, they are selected and evaluated automatically by
interpreting the physical address. No additional switching or selecting is necessary
during run time, except when more than the four address windows plus the default is to
be used.
Switching from demultiplexed to multiplexed bus mode represents a special case.
The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1
as usual, if another BUSCON register selects a demultiplexed bus. However, in the
multiplexed bus modes the address is also required on PORT0. In this special case the
address on PORT0 is delayed by one CPU clock cycle, which delays the complete
(multiplexed) bus cycle and extends the corresponding ALE signal (see figure below).
This extra time is required to allow the previously selected device (via demultiplexed bus)
to release the data bus, which would be available in a demultiplexed bus cycle.
Data Sheet
instruction stream. Due to the internal pipelining it is very difficult to determine the
first instruction fetch that will use the new configuration. Only change the
configuration for address areas that are not currently accessed. This applies to
BUSCON registers as well as to ADDRSEL registers.
163
The External Bus Interface
PSB 21473
2003-03-31
INCA-D