PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 533

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

In general, three criteria for buffer switching are implemented in the USB module :
22.4.4
A running data transfer to or from one of the FIFO buffers must not be interrupted to
ensure a correct handling of the address pointer defined by ADROFFn.
Therefore all USB Endpoint related interrupts must be blocked while one of the FIFOs is
currently accessed within an invoked InterruptServiceRoutine. For Endpoints 0 and 5-15
this is automatically realized, because they use the combined interrupt USBEPINT (see
Figure 8-2).
Data Sheet
a) For sequential access, the address offset register ADROFFn is automatically
b) When Bit DONE, which is located in the endpoint buffer status register EPBSn, is
c) The third criteria for buffer switching is the automatic buffer switching on detection
incremented after each read or write action of the CPU. The address offset value
(before incrementing) represents the number of bytes stored in USB memory for a
specific endpoint. If the address offset value (after incrementing) reaches the value
stored in endpoint length register EPLENn, the currently active buffer is tagged full
(USB read access - all bytes have been written by CPU, CBF=1) or empty (USB
write access - all bytes have been read by CPU, CBF=0).
set, software buffer switching is initiated. This action is independent from the
number of bytes which have been handled by the CPU (possible in sequential
access mode (INCE=1) and random access mode (INCE=0)).
On CPU read accesses, the buffer is declared empty and bit CBF is cleared. If the
buffer assigned to the USB is full (UBF=1), the buffers are immediately swapped.
In this case, register EPLENn contains the number of received bytes.
On CPU write accesses, two different cases must be distinguished. For random
accesses, the number of bytes of one packet is fixed by the value in register
EPLENn and does not change. For sequential accesses, the number of written
bytes represents the packet size. In this case, the actual value of register
ADROFFn is transferred to register EPLENn when bit DONE is set.
of SOF (see figure 22-17). This feature can be individually enabled (SOFDE=1) or
disabled (SOFDE=0) by software selectively for each endpoint.
Interruption of data transfers
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USB Module
PSB 21473
2003-03-31
INCA-D