PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 40

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
Memory Organization
5
Memory Organization
The memory space of the INCA-D is configured in a “Von Neumann” architecture. This
means that code and data are accessed within the same linear address space. All of the
physically separated memory areas, including internal Dual-Port RAM with the internal
Special Function Register Areas (SFRs and ESFRs), the address areas for integrated
XBUS peripherals and external memory are mapped into one common address space.
Generally, the CPU core of the INCA-D provides a total addressable memory space of
16 MBytes. This address space is arranged as 256 segments of 64 KBytes each, and
each segment is again subdivided into four data pages of 16 KBytes each
However, the addressable external memory space of the INCA-D is limited to 4
1)
MBytes
.
Bytes are stored at even or odd byte addresses. Words are stored in ascending memory
locations with the low byte at an even byte address being followed by the high byte at
the next odd byte address. Double words (code only) are stored in ascending memory
locations as two subsequent words. Single bits are always stored in the specified bit
position at a word address. Bit position 0 is the least significant bit of the byte at an even
byte address, and bit position 15 is the most significant bit of the byte at the next odd
byte address. Bit addressing is supported for a part of the Special Function Registers, a
part of the internal RAM and for the General Purpose Registers.
Figure 5-1
Storage of Words, Byte and Bits in a Byte Organized Memory
1)
Each of the 2 chip selects can be used to access a 4 MB window of memory
Data Sheet
40
2003-03-31