PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 265

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
The High-Speed Synchronous Serial Interfaces
• select the clock idle level (SSCxPO=’x’)
• load the port output latch with the desired clock idle level
• switch the pin to output
• enable the SSC (SSCxEN=’1’)
• if SSCxPO=’0’: enable alternate data output
The same mechanism as for selecting a slave for transmission (separate select lines or
special commands) may also be used to move the role of the master to another device
in the network. In this case the previous master and the future master (previous slave)
will have to toggle their operating mode (SSCxMS) and the direction of their port pins
(see description above).
16.2
Half Duplex Operation
In a half duplex configuration only one data line is necessary for both receiving and
transmitting of data. The data exchange line is connected to both pins MTSRx and
MRSxT of each device, the clock line is connected to the SCLKx pin.
The master device controls the data transfer by generating the shift clock, while the slave
devices receive it. Due to the fact that all transmit and receive pins are connected to the
one data exchange line, serial data may be moved between arbitrary stations.
Similar to full duplex mode there are two ways to avoid collisions on the data
exchange line:
• only the transmitting device may enable its transmit pin driver
• the non-transmitting devices use open drain output and only send ones.
Since the data inputs and outputs are connected together, a transmitting device will clock
in its own data at the input pin (MRSTx for a master device, MTSRx for a slave). By these
means any corruptions on the common data exchange line are detected, where the
received data is not equal to the transmitted data.
Data Sheet
265
2003-03-31