PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 585

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Figure 23-1 Transitions between Idle mode and active mode
Idle mode can also be terminated by a Non-Maskable Interrupt, ie. a high to low transition
on the NMI pin. After Idle mode has been terminated by an interrupt or NMI request, the
interrupt system performs a round of prioritization to determine the highest priority
request. In the case of an NMI request, the NMI trap will always be entered.
Any interrupt request whose individual Interrupt Enable flag was set before Idle mode
was entered will terminate Idle mode regardless of the current CPU priority. The CPU
will not go back into Idle mode when a CPU interrupt request is detected, even when the
interrupt was not serviced because of a higher CPU priority or a globally disabled
interrupt system (IEN=’0’). The CPU will only go back into Idle mode when the interrupt
system is globally enabled (IEN=’1’) and a PEC service on a priority level higher than
the current CPU level is requested and executed.
Note: An interrupt request which is individually enabled and assigned to priority level 0
The watchdog timer may be used to monitor the Idle mode: an internal reset will be
generated if no interrupt or NMI request occurs before the watchdog timer overflows. To
prevent the watchdog timer from overflowing during Idle mode it must be programmed
to a reasonable time interval before Idle mode is entered.
23.3
To further reduce the power consumption the microcontroller can be switched to Power
Down mode. Clocking of all internal blocks is stopped, the contents of the internal RAM,
however, are preserved through the voltage supplied via the V
timer is stopped in Power Down mode. This mode can only be terminated by an external
hardware reset, ie. by asserting a low level on the RSTIN pin. This reset will initialize all
Data Sheet
will terminate Idle mode. The associated interrupt vector will not be accessed,
however.
Power Down Mode of the CPU
Active
Mode
CPU Interrupt Request
Denied PEC Request
IDLE instruction
585
denied
accepted
Power Reduction Modes
DD
Mode
pins. The watchdog
Idle
PSB 21473
PEC Request
Executed
2003-03-31
INCA-D