PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 294

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
IOM-2 Handler, TIC/CI Handler and HDLC Controller
In case of an access request, the Bus Accessed-bit BAC (bit 5 of last octet of CH2 on
DU) is checked for the status ’bus free’, which is indicated by a logical ’1’. If the bus is
free, the individual TIC bus address TAD programmed in the CIX0 register (CIX0:TBA2-
0) is transmitted. While being transmitted the TIC bus address TAD is compared bit by
bit with the value read back from DU. If a sent bit set to ’1’ is read back as ’0’ because of
the access of another D-channel source with a lower TAD, the TIC bus access is
immediately withdrawn, i.e. the remaining TAD bits are not transmitted. The TIC bus is
occupied by the device which sends and reads back its address error-free. If more than
one device attempt to seize the bus simultaneously, the one with the lowest address
values wins. This one will set BAC=0 on TIC bus and start D-channel transmission.
DU
Figure 1
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized, the bus is identified to other devices as occupied via the DU
Ch2 Bus Accessed-bit state ’0’ until the access request is withdrawn. After a successful
bus access, the device is automatically set into a lower priority class, that is, a new bus
access cannot be performed until the status "bus free" is indicated in two successive
frames.
If none of the devices connected to the IOM interface request access to the D and C/I
channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the P when access to the C/I channels
is no more requested, to grant other devices access to the D and C/I channels.
Data Sheet
294
2003-03-31