MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 104

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

System Integration Module (SIM)
7.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter.
free-running after all reset states.
internal reset recovery sequences.)
7.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
7.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing, and
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
(See
104
INTERRUPT
INTERRUPT
•
•
•
MODULE
MODULE
Figure
I-BIT
I-BIT
Interrupts:
–
–
Reset
Break interrupts
R/W
R/W
IAB
IDB
IAB
IDB
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
7-10.)
DUMMY
DUMMY
Figure 7-9
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
Figure 7-9. Interrupt Recovery Timing
CCR
(See 7.3.2 Active Resets from Internal Sources
MC68HC908AP Family Data Sheet, Rev. 4
Figure 7-8. Interrupt Entry Timing
SP – 1
SP – 3
shows interrupt recovery timing.
A
SP – 2
SP – 2
(See 7.6.2 Stop Mode
X
X
SP – 3
SP – 1
PC – 1[15:8] PC – 1[7:0]
A
SP – 4
SP
CCR
VECT H
PC
for details.) The SIM counter is
V DATA H
OPCODE
VECT L
PC + 1
OPERAND
V DATA L
for counter control and
Figure 7-8
Freescale Semiconductor
START ADDR
OPCODE
shows