MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 43

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

2.5.2 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operation.
HVEN — High Voltage Enable Bit
MASS — Mass Erase Control Bit
ERASE — Erase Control Bit
PGM — Program Control Bit
2.5.3 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 512 consecutive
bytes starting from addresses $X000, $X200, $X400, $X600, $X800, $XA00, $XC00, or $XE00. The
48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons.
Mass erase is required to erase this page.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
Freescale Semiconductor
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Write any data to any FLASH location within the page address range desired.
3. Wait for a time, t
4. Set the HVEN bit.
5. Wait for a time t
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
This read/write bit configures the memory for mass erase operation or page erase operation when the
ERASE bit is set.
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1 = Mass erase operation selected
0 = Page erase operation selected
1 = Erase operation selected
0 = Erase operation not selected
1 = Program operation selected
0 = Program operation not selected
Address:
Reset:
Read:
Write:
erase
$FE08
nvs
Bit 7
0
0
(5 µs).
(20 ms).
Figure 2-3. FLASH Control Register (FLCR)
6
0
0
MC68HC908AP Family Data Sheet, Rev. 4
5
0
0
4
0
0
HVEN
3
0
MASS
2
0
ERASE
1
0
PGM
Bit 0
0
FLASH Memory
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