MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 276

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

External Interrupt (IRQ)
The IRQ1 pin has a permanent internal pullup device connected, while the IRQ2 pin has an optional
pullup device that can be enabled or disabled by the PUC0ENB bit in the INTSCR2 register.
17.5 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during
the break state. (See
To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE bit. With BCFE at logic
0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has
no effect on the IRQ interrupt flags.
17.6 IRQ Registers
Each IRQ is controlled and monitored by an status and control register.
17.6.1 IRQ1 Status and Control Register
The IRQ1 status and control register (INTSCR1) controls and monitors operation of IRQ1. The INTSCR1
has the following functions:
IRQ1F — IRQ1 Flag Bit
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
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This read-only status bit is high when the IRQ1 interrupt is pending.
Writing a logic 1 to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic 0. Reset clears
ACK1.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
IRQ1 Status and Control Register
IRQ2 Status and Control Register
Shows the state of the IRQ1 flag
Clears the IRQ1 latch
Masks IRQ1 interrupt request
Controls triggering sensitivity of the IRQ1 interrupt pin
Address:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
Reset:
Read:
Write:
Figure 17-4. IRQ1 Status and Control Register (INTSCR1)
Chapter 21 Break Module
$001E
Bit 7
0
0
= Unimplemented
6
0
0
MC68HC908AP Family Data Sheet, Rev. 4
— $001E
— $001C
5
0
0
(BRK).)
NOTE
4
0
0
IRQ1F
3
0
ACK1
2
0
0
IMASK1
1
0
Freescale Semiconductor
MODE1
Bit 0
0