MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 33

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

† One-time writable register after each reset.
† One-time writable register after each reset.
Freescale Semiconductor
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
Addr.
IRQ2 Status and Control Reg-
IRQ1 Status and Control Reg-
Timer 1 Counter Modulo Reg-
Timer 1 Channel 0 Status and
Keyboard Status and Control
Control Register (T1SC0)
Configuration Register 2
Configuration Register 1
Timer 1 Counter Modulo
Register Name
Timer 1 Status and
Keyboard Interrupt
Control Register
Timer 1 Counter
Timer 1 Counter
Enable Register
U = Unaffected
Register High
Register Low
Register Low
(CONFIG2)
(CONFIG1)
(INTSCR2)
(INTSCR1)
(T1MODH)
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
(T1MODL)
(T1CNTH)
(T1CNTL)
ister High
(KBSCR)
Register
(KBIER)
(T1SC)
ister
ister
†
†
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
X = Indeterminate
MC68HC908AP Family Data Sheet, Rev. 4
ICLKDIS
COPRS
STOP_
KBIE7
Bit 15
Bit 15
CH0F
Bit 7
TOF
Bit 7
Bit 7
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
PUC0ENB
LVISTOP
RCLKEN
STOP_
CH0IE
KBIE6
TOIE
14
14
6
0
0
0
0
0
0
0
0
0
0
6
0
1
6
1
0
LVIRSTD
XCLKEN
TSTOP
STOP_
KBIE5
MS0B
13
13
5
0
0
0
0
0
0
0
0
0
1
0
5
0
1
5
1
0
= Unimplemented
OSCCLK1 OSCCLK0
LVIPWRD
KBIE4
MS0A
TRST
12
12
4
0
0
0
0
0
0
0
0
0
0
0
0
4
0
1
4
1
0
LVIREGD
ELS0B
KBIE3
IRQ2F
IRQ1F
KEYF
11
11
3
0
0
0
0
0
0
0
0
0
3
0
1
3
1
0
SSREC
ELS0A
KBIE2
ACK2
ACK1
ACK
PS2
10
10
R
2
0
0
0
0
0
0
0
0
0
0
0
0
2
0
1
2
1
0
= Reserved
IMASK2
IMASK1
IMASK
KBIE1
STOP
TOV0
PS1
1
0
0
0
0
0
0
0
0
9
0
1
0
9
1
1
1
0
Monitor ROM
SCIBDSRC
CH0MAX
MODE2
MODE1
MODE
KBIE0
COPD
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PS0
0
0
0
0
0
0
0
0
0
1
1
0
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