MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 93

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

6.5.5 PLL Reference Divider Select Register
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
RDS[3:0] — Reference Divider Select Bits
6.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the divided VCO clock, CGMPCLK, divided by
two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the
Freescale Semiconductor
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See
Clock Selector Circuit
$40 for a default range multiply value of 64.
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See
bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference
divider the same as a value of $01. (See
register to $01 for a default divide value of 1.
6.3.3 PLL Circuits
Address:
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
Reset:
Read:
Write:
Figure 6-9. PLL Reference Divider Select Register (PMDS)
$003B
Bit 7
0
0
and
and
6.3.7 Special Programming
6.3.6 Programming the
=
Unimplemented
6
0
0
MC68HC908AP Family Data Sheet, Rev. 4
5
0
0
6.3.7 Special Programming
NOTE
NOTE
NOTE
4
0
0
PLL.) RDS[3:0] cannot be written when the PLLON
Exceptions.). Reset initializes the register to
RDS3
3
0
RDS2
2
0
Exceptions.) Reset initializes the
RDS1
1
0
RDS0
Bit 0
1
6.3.8 Base
Interrupts
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