MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 256

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Analog-to-Digital Converter (ADC)
15.7.2 ADC Clock Control Register
The ADC clock control register (ADICLK) selects the clock frequency for the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
254
ADCH4
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
Table 15-2
and 1MHz.
the ADC converter both in production test and for user applications.
0
0
0
0
0
0
0
0
0
↓
1
1
1
1
Address:
shows the available clock configurations. The ADC clock should be set to between 500 kHz
ADCH3
Reset:
Read:
Write:
0
0
0
0
0
0
0
0
1
↓
1
1
1
1
ADIV2
$0058
0
Figure 15-4. ADC Clock Control Register (ADICLK)
ADCH2
0
0
0
0
1
1
1
1
0
↓
1
1
1
1
= Unimplemented
ADIV1
0
MC68HC908AP Family Data Sheet, Rev. 4
Table 15-1. MUX Channel Select
ADCH1
ADIV0
↓
0
0
1
1
0
0
1
1
0
0
0
1
1
0
ADICLK
ADCH0
0
↓
0
1
0
1
0
1
0
1
0
0
1
0
1
MODE1
R
0
ADC powered-off
ADC Channel
ADC28
ADC29
ADC30
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
= Reserved
MODE0
↓
1
0
0
Freescale Semiconductor
V
V
REFH
REFL
Input Select
Reserved
R
0
0
(see Note 2)
(see Note 2)
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
—