MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 242

no-image

MC908AP32CFBE

Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet

Specifications of MC908AP32CFBE

Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908AP32CFBE
Manufacturer:
Freescale
Quantity:
6
Part Number:
MC908AP32CFBE
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
MC908AP32CFBE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908AP32CFBE
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
MC908AP32CFBE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC908AP32CFBE
Quantity:
96
Part Number:
MC908AP32CFBER
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
MC908AP32CFBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Multi-Master IIC Interface (MMIIC)
14.6.7 MMIIC CRC Data Register (MMCRCDR)
When the MMIIC module is enabled, MMEN = 1, and the CRC buffer full flag is set (MMCRCBF = 1), data
in this read-only register contains the generated CRC byte for the last byte of received or transmitted data.
A CRC byte is generated for each received and transmitted data byte and loaded to the CRC data
register. The MMCRCBF bit will be set to indicate the CRC byte is ready in the CRC data register.
Reading the CRC data register clears the MMCRCBF bit. If the CRC data register is not read, the
MMCRCBF bit will be cleared by hardware before the next CRC byte is loaded.
14.6.8 MMIIC Frequency Divider Register (MMFDR)
The three bits in the frequency divider register (MMFDR) selects the divider to divide the bus clock to the
desired baud rate for the MMIIC data transfer.
Table 14-2
240
shows the divider values for MMBR[2:0].
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 14-11. MMIIC Frequency Divider Register (MMFDR)
MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
$004E
$004F
Bit 7
Bit 7
Figure 14-10. MMIIC CRC Data Register (MMCRCDR)
0
0
0
= Unimplemented
= Unimplemented
6
0
6
0
0
MC68HC908AP Family Data Sheet, Rev. 4
5
0
5
0
0
4
0
4
0
0
3
0
3
0
0
MMBR2
2
0
2
1
MMBR1
1
0
1
0
Freescale Semiconductor
MMBR0
Bit 0
Bit 0
0
0

Related parts for MC908AP32CFBE