MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 241
MC908AP32CFBE
Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet
1.MC908AP32CFBE.pdf
(324 pages)
Specifications of MC908AP32CFBE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether
module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit when:
If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA
line for master to generate a STOP or repeated START condition. The data in the MMDTR will not be
transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains
cleared (MMTXBE = 0).
In master mode, the data in MMDTR will be transferred to the output circuit when:
If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a STOP or
repeated START condition. The data in the MMDTR will not be transferred to the output circuit. The
transmit buffer empty flag remains cleared (MMTXBE = 0).
The sequence of events for slave transmit and master transmit are illustrated in
14.6.6 MMIIC Data Receive Register (MMDRR)
When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether
module is in master or slave mode.
In slave mode, the data in MMDRR is:
In master mode, the data in the MMDRR is:
When the MMDRR is read by the CPU, the receive buffer full flag is cleared (MMRXBF = 0), and the next
received data is loaded to the MMDRR. Each time when new data is loaded to the MMDRR, the MMRXIF
interrupt flag is set, indicating that new data is available in MMDRR.
The sequence of events for slave receive and master receive are illustrated in
Freescale Semiconductor
•
•
•
•
•
•
•
the module detects a matched calling address (MMATCH = 1), with the calling master requesting
data (MMSRW = 1); or
the previous data in the output circuit has be transmitted and the receiving master returns an
acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
the module receives an acknowledge bit (MMRXAK = 0), after
setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or
the previous data in the output circuit has be transmitted and the receiving slave returns an
acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
the calling address from the master when the address match flag is set (MMATCH = 1); or
the last data received when MMATCH = 0.
the last data received.
Address:
Reset:
Read:
Write:
MMRD7
$004D
Bit 7
Figure 14-9. MMIIC Data Receive Register (MMDRR)
0
= Unimplemented
MMRD6
6
0
MC68HC908AP Family Data Sheet, Rev. 4
MMRD5
5
0
MMRD4
4
0
MMRD3
3
0
MMRD2
2
0
MMRD1
1
0
Figure
Figure
MMRD0
14-12.
MMIIC I/O Registers
Bit 0
14-12.
0
239
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