MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 92

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Clock Generator Module (CGM)
6.5.3 PLL Multiplier Select Registers
The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the
modulo feedback divider.
MUL[11:0] — Multiplier Select Bits
6.5.4 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
VRS[7:0] — VCO Range Select Bits
92
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier N.
(See
registers configure the modulo feedback divider the same as a value of $0001. Reset initializes the
registers to $0040 for a default multiply value of 64.
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (See
hardware center-of-range frequency, f
PCTL is set. (See
6.3.3 PLL Circuits
6.3.3 PLL
Address:
Address:
Address:
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Circuits,
6.3.7 Special Programming
Figure 6-6. PLL Multiplier Select Register High (PMSH)
$003A
$0038
$0039
Figure 6-7. PLL Multiplier Select Register Low (PMSL)
MUL7
VRS7
Bit 7
Bit 7
Bit 7
Figure 6-8. PLL VCO Range Select Register (PMRS)
0
0
0
0
and
6.3.6 Programming the
= Unimplemented
6.3.6 Programming the
MUL6
VRS6
6
0
0
6
1
6
1
MC68HC908AP Family Data Sheet, Rev. 4
MUL5
VRS
VRS5
5
0
0
5
0
5
0
. VRS[7:0] cannot be written when the PLLON bit in the
NOTE
Exceptions.) A value of $00 in the VCO range select
MUL4
VRS4
4
0
0
4
0
4
0
PLL, and
PLL.) A value of $0000 in the multiplier select
MUL11
MUL3
VRS3
3
0
3
0
3
0
6.5.1 PLL Control
MUL10
MUL2
VRS2
2
0
2
0
2
0
MUL9
MUL1
VRS1
1
0
1
0
1
0
Register.), controls the
Freescale Semiconductor
MUL8
MUL0
VRS0
Bit 0
Bit 0
Bit 0
0
0
0