SR2400PP Intel, SR2400PP Datasheet - Page 124

• Manufacturer Part Number: SR2400PP
• Manufacturer: Intel

Specifications of SR2400PP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Error Reporting and Handling
6.
This section defines how errors are handled. Also discussed is the role of the BIOS in error
handling and the interaction between the BIOS, platform hardware, and server management
firmware with regard to error handling. In addition, error-logging techniques are described and
beep codes and POST messages are defined.
6.1
Fault Resilient Booting (FRB) is a set of BIOS and BMC algorithms and hardware support that
allow a multiprocessor system to boot in case of failure of the bootstrap processor (BSP) under
certain conditions.
With on-board platform instrumentation, should a processor failure be detected during POST,
the mBMC does not have the ability to disable the failed or failing processor. Therefore the
system may or may not continue to boot. An FRB-2 error will be logged in the System Event Log
(SEL) and an error will be displayed at POST. FRB2 is a BIOS-based algorithm that uses the
mBMC IPMI watchdog timer to protect against BIOS hangs during the POST process
6.1.1
The BIOS provides an FRB1 timer. Early in POST, the BIOS checks the Built-in Self Test (BIST)
results of the BSP. If the BSP fails BIST, the BIOS will notify the user that the BIST failed; no
processors will be disabled.
The BIST failure is displayed during POST and an error is logged to the SEL.
6.1.2
A second timer (FRB2) is set to several minutes by BIOS and is designed to guarantee that the
system completes POST. The FRB2 timer is enabled just before the FRB3 timer is disabled to
prevent any “unprotected” window of time. Near the end of POST, the BIOS disables the FRB2
timer. If the system contains more than 1 GB of memory and the user chooses to test every
DWORD of memory, the watchdog timer is extended before the extended memory test starts,
because the memory test can exceed the timer duration. The BIOS will also disable the
watchdog timer before prompting the user for a boot password. If the system hangs during
POST, before the BIOS disables the FRB2 timer, the appropriate event will be logged in the
System Event Log (SEL), and displayed to the user.
The BIOS provides options to control the policy applied to FRB2 failures. These options are not
supported by the Server Board SE7320VP2, and mBMC does not support the option to disable
the BSP.
124
Error Reporting and Handling
Fault Resilient Booting (FRB)
FRB1 – BSP Self-Test Failures
FRB2 – BSP POST Failures
Intel order number C91056-002
Intel® Server Board SE7320VP2
Revision 2.1