SR2400PP Intel, SR2400PP Datasheet - Page 142

• Manufacturer Part Number: SR2400PP
• Manufacturer: Intel

Specifications of SR2400PP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Error Reporting and Handling
Checkpoint
A1
A2
A4
A7
A8
A9
AA
AB
AC
B1
00
6.5.4
The Bootblock initialization code sets up the chipset, memory and other components before
system memory is available. The following table describes the type of checkpoints that may
occur during the bootblock initialization portion of the BIOS:
Checkpoint
Before D1
D1
D0
D2
D3
D4
D5
142
Bootblock Initialization Code Checkpoints
MSB
MSB
G=Green, R=Red, A=Amber
OFF
G=Green, R=Red, A=Amber
Diagnostic LED Decoder
Diagnostic LED Decoder
R
R
R
R
A
A
A
A
A
R
R
R
R
R
R
R
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
G
G
G
R
R
R
R
A
A
Table 76. Bootblock Initialization Code Checkpoints
OFF
OFF
OFF
OFF
OFF
R
R
R
R
R
R
G
G
A
A
A
A
LSB
OFF
OFF
OFF
OFF
OFF
OFF
LSB
Intel order number C91056-002
G
G
G
G
A
A
R
R
A
R
A
Passes control to OS Loader (typically INT19h).
Clean-up work needed before booting to operating system.
Takes care of runtime image preparation for different BIOS modules.
Fill the free area in F000h segment with 0FFh. Initializes the Microsoft
IRQ Routing Table. Prepares the runtime language module. Disables
the system configuration display if needed.
Initialize runtime language module.
Displays the system configuration screen if enabled. Initialize the
CPU’s before boot, which includes the programming of the MTRR’s.
Prepare CPU for operating system boot including final MTRR values.
Wait for user input at config display if needed.
Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the
ADM module.
Prepare BBS for Int 19 boot.
End of POST initialization of chipset registers.
Save system context for ACPI.
Early chipset initialization is done. Early super I/O initialization is done
including RTC and keyboard controller. NMI is disabled.
Perform keyboard controller BAT test. Check if waking up from power
management suspend state. Save power-on CPUID value in scratch
CMOS.
Go to flat mode with 4GB limit and GA20 enabled. Verify the
bootblock checksum.
Disable CACHE before memory detection. Execute full memory sizing
module. Verify that flat mode is enabled.
If memory sizing module not executed, start memory refresh and do
memory sizing in Bootblock code. Do additional chipset initialization.
Re-enable CACHE. Verify that flat mode is enabled.
Test base 512KB memory. Adjust policies and cache first 8MB. Set
stack.
Bootblock code is copied from ROM to lower system memory and
control is given to it. BIOS now executes out of RAM.
Description
Description
Intel® Server Board SE7320VP2
Revision 2.1