SR2400PP Intel, SR2400PP Datasheet - Page 127

• Manufacturer Part Number: SR2400PP
• Manufacturer: Intel

Specifications of SR2400PP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
6.2.2
If the memory RAS feature is not enabled in BIOS Setup, the BIOS will apply the “10 SBE errors
in one hour” implementation (memory error logging will be disabled if (10) SBE’s occur in one
hour). Enabling this implementation and RAS feature are mutually-exclusive and automatically
handled by system BIOS.
In non-RAS mode, BIOS maintains a counter for Single Bit ECC (SBE) errors. If ten SBE errors
occur within an hour, BIOS will disable SBE detection in the chipset to prevent the System
Event Log (SEL) from being filled up, and the operating system from being halted.
In non-RAS mode, BIOS will assert a Non-Maskable-Interrupt (NMI) on the first double-bit ECC
(DBE) error.
6.2.3
Setting the “Memory Retest” option to “Enabled” in BIOS Setup will bring all DIMM(s) back on
line regardless of current states. After replacing faulty DIMM(s), the “Memory Retest” option
must be set to “Enabled”.
Note: This step is not required if faulty DIMM(s) is not taken off-line.
6.2.4
The system detects, corrects, and logs correctable errors. As long as these errors occur
infrequently, the system should continue to operate without a problem.
Occasionally, correctable errors are caused by a persistent failure of a single component. For
example, a broken data line on a DIMM would exhibit repeated errors until replaced. Although
these errors are correctable, continual calls to the error logger can throttle the system,
preventing any further useful work.
For this reason, the system counts certain types of correctable errors and disables reporting if
they occur too frequently. Correction remains enabled but calls to the error handler are
disabled. This allows the system to continue running, despite a persistent correctable failure.
The BIOS adds an entry to the event log to indicate that logging for that type of error has been
Revision 2.1
Memory Error Handling in non-RAS Mode
DIMM Enabling
Single-bit ECC Error Throttling Prevention
Single Bit ECC (SBE) errors
Double Bit ECC (DBE) errors
Table 60. Memory Error Handling in Non-RAS mode
Non-RAS mode
Intel order number C91056-002
SBE error events will not be logged.
On the 10th SBE error, BIOS will:
- Disable SBE detection in chipset.
- Light the faulty DIMM LED.
On the 1st DBE error, BIOS will:
- Log DBE record to the SEL.
- Light the faulty DIMM LED.
- Generate NMI.
Server Board SE7320VP2
Error Reporting and Handling
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