SR2400PP Intel, SR2400PP Datasheet - Page 129

• Manufacturer Part Number: SR2400PP
• Manufacturer: Intel

Specifications of SR2400PP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
on the primary interface whenever there is a SERR# on the secondary side, if SERR# has been
enabled through Setup. The same is true for PERR#.
6.3.1.2
If the chipset supports ECC on the processor bus then the BIOS enables the error correction
and detection capabilities of the processors by setting appropriate bits in the processor model
specific register (MSR) and appropriate bits inside the chipset.
In the case of irrecoverable errors on the host processor bus, proper execution of the
asynchronous error handler (usually SMI) cannot be guaranteed and the handler cannot be
relied upon to log such conditions. The handler will record the error to the SEL only if the
system has not experienced a catastrophic failure that compromises the integrity of the handler.
6.3.1.3
The hardware is programmed to generate an SMI on single-bit data errors in the memory array
if ECC memory is installed. The SMI handler records the error and the DIMM location to the
system event log. Double-bit errors in the memory array are mapped to the SMI because the
mBMC cannot determine the location of the bad DIMM. The double-bit errors may have
corrupted the contents of SMRAM. The SMI handler will log the failing DIMM number to the
mBMC if the SMRAM contents are still valid. The ability to isolate the failure down to a single
DIMM may not be available on certain platforms, and/or during early POST.
6.3.1.4
The mBMC monitors system operational limits. It manages the A/D converter, defining voltage
and temperature limits as well as fan sensors and chassis intrusion. Any sensor values outside
of specified limits are fully handled by the mBMC. The BIOS does not generate an SMI to the
host processor for these types of system events.
6.3.1.5
The BIOS detects any processor BIST failures and logs the event. The failed processor can be
identified by the first OEM data byte field in the log. For example, if processor 0 fails, the first
OEM data byte will be 0. The BIOS depends upon the mBMC to log the watchdog timer reset
event.
If an operating system device driver is using the watchdog timer to detect software or hardware
failures and that timer expires, an Asynchronous Reset (ASR) is generated, which is equivalent
to a hard reset. The POST portion of the BIOS can query the BMC for a watchdog reset event
as the system reboots, and then log this event in the SEL.
6.3.1.6
The BIOS downloads the system date and time to the mBMC during POST and logs a boot
event. This record does not indicate an error, and software that parses the event log should
treat it as such.
Revision 2.1
Processor Bus Error
Memory Bus Error
System Limit Error
Processor Failure
Boot Event
Intel order number C91056-002
Error Reporting and Handling
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