TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 148

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

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PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
12.9.2 Boundary Scan Operation
12.9.3 Boundary Scan Reset
The TAP controller receives external control information via a Test Clock (TCK) signal and a
Test Mode Select (TMS) signal, and sends control signals to the internal scan paths. Detailed
information on the operation of this state machine can be found in the IEEE 1149.1 standard.
The serial scan path architecture consists of an instruction register, a boundary scan register
and a bypass register. These three serial registers are connected in parallel between the Test
Data Input (TDI) and Test Data Output (TDO) signals, as shown in
The boundary scan function can be reset and disabled by holding lead TRS low. When
boundary scan testing is not being performed the boundary scan register is transparent,
allowing the input and output signals to pass to and from the PHAST-12N device’s internal
logic. During boundary scan testing, the boundary scan register may disable the normal flow
of input and output signals to allow the device to be controlled and observed via scan opera-
tions.
The maximum frequency the PHAST-12N device will support for boundary scan is 10 MHz.
The timing diagrams for the boundary scan interface leads are shown in
The instruction register contains three bits. The PHAST-12N device performs the following
three boundary scan test instructions:
Specific control of the TRS lead is required in order to ensure that the boundary scan logic
does not interfere with normal device operation. This lead must either be held low, asserted
low, or asserted low then high (pulsed low), to asynchronously reset the Test Access Port
(TAP) controller during power-up of the PHAST-12N. If boundary scan testing is to be
performed and the lead is held low, then a pull-down resistor value must be chosen which will
allow the tester to drive this lead high, but still meet the V
Output and Input/Output Parameters’ section of this Data Sheet for worst case leakage
currents of all devices sharing this pull-down resistor.
The EXTEST test instruction (000) provides the ability to test the connectivity
of the PHAST-12N device to external circuitry.
The SAMPLE test instruction (010) provides the ability to examine the bound-
ary scan register contents without interfering with device operation.
The BYPASS test instruction (111) provides the ability to bypass the PHAST-
12N boundary scan and instruction registers.
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Telecom Bus
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IL
requirements listed in the ‘Input,
Figure
Figure
54.
54.
1 4 8 o f 2 0 2