TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 87

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8 7 o f 2 0 2
10.2 CLOCK ARCHITECTURE
Note 1: These Is_TUG_Structured configuration registers need only be specified for the Add
and the Drop Telecombus interfaces and are don’t care for all other interfaces.
Note 2: V1 pulses will be enabled on the Telecombus interfaces when the structures contain
TUG-2’s (see
The PHAST-12N’s internal Transmit Clock synthesizer generates, using a selectable Tx
timebase, a high-speed Transmit Clock, running at 622.08 MHz.
The System Clock, running at 77.76 MHz, is a divided-down version of this high-speed
Transmit Clock.
Telecom Bus clocks:
The System Clock is available on an output lead: LINETXCLK, optionally divided down to
19.44 MHz.
The PHAST-12N’s internal Clock Recovery units, operating on the four SDH/SONET Receive
Line interfaces and the Receive APS Port generate five recovered clocks: one for each channel.
Internally, these units require a high-speed Receive Clock, which is synthesized using a
selectable Rx timebase.
The recovered data from the four SDH/SONET Receive Lines and from the Receive APS
Port is retimed to the System Clock, before entering the Cross Connect.
Divided-down versions of each recovered clock are available on output leads: LINERXCLK1
(19.44 or 77.76 MHz), LINERXCLK2 (19.44 MHz), LINERXCLK3 (19.44 MHz), LINERXCLK4
(19.44 MHz), and APSRXCLK (19.44 or 77.76 MHz).
The Tx timebase can be selected using control bits:
• The Drop Telecom Bus clock output lead, CBDPCLK, is actually the System Clock
• The Add Telecom Bus clock lead, CBADCLK, is an output in master timing mode. It is
• The Add Telecom Bus clock lead, CBADCLK, is an input in slave timing mode. It gets
• Either one of the two external Transmit Clock sources: REFTXCLK1 or REFTXCLK2P/N
• The recovered 622.08 MHz Receive APS Port clock (External Timing) (control field:
Is_TUG_Structured
actually the System Clock
retimed to the System Clock in the Retimer
(External Timing) (control field TxRefSelect, see
Descriptions)
LineTimingChannel and TimingMode, see
Descriptions)
1 (Default)
Telecom Bus Interface
0
[timeslot]
- Operation -
section).
• C-3 is mapped in VC-3 (AU-3 mode)
• TU-3 is mapped in TUG-3 (AU-4 mode)
• TUG-2 is mapped in VC-3 (AU-3 mode)
• TUG-2 is mapped in TUG-3 (AU-4 mode)
Table 55
Description
Table 55
PRELIMINARY TXC-06312B-MB, Ed. 2
of the
of the
PHAST-12N Device
Memory Maps and Bit
Memory Maps and Bit
DATA SHEET
TXC-06312B
June 2005