TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 47

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4 7 o f 2 0 2
7.4 POWER SUPPLY SHARING, FILTERING AND OTHER REQUIREMENTS
7.5 LVPECL I/O RECOMMENDATIONS:
VDD33 may be combined with other 3.3V card supplies.
VDDA33LVPCDRV and VDDA33LVPCIO may share a supply, but should each be filtered.
VDDA33LVPCDRV must use the same supply as the Tx side of the optical transceiver(s)
(also filtered), for LVPECL threshold tracking.
VREF should have an isolated 1.2V supply.
VTERM (optional) should have an isolated 1.2V supply, when used.
All VSS pins may be combined on a strong ground plane with appropriate decoupling.
The following power pins supply I/O ESD structures and must either lead other supplies or be
simultaneous with other supplies: VDD33 and VDDA33LVPCIO.
Device inputs may not be driven until the core supplies are up.
The use of VREF is mandatory. It is the reference voltage for the four LVPECL Tx pads
(LINETXDATA1P/N, LINETXDATA2P/N, LINETXDATA3P/N, LINETXDATA4P/N) and the
LVDS Tx pad (APSTXDATAP/N). In addition, it is used to bias the Rx and Tx PLLs.
The use of VTERM is optional, and in fact not recommended: It serves as the termination
voltage for the LVDS Rx pad (APSRXDATAP/N).
VTERM must only be supplied, when the potential difference between the grounds of the two
PHAST-12N devices (connected using the APS port) is large and does not meet LVDS
standard: [IEEE Std 1596.3-1996]. In this case, the VTERM current can get larger than
20mA. If the grounds are equal, no current will be drawn and VTERM is not needed (can be
left floating).
When the APS port is not used, VTERM can be left floating as well.
VDD18 may be combined with other 1.8V card supplies, but should be each filtered.
VDDA18TPA supplies the Tx PLL / Clock Synthesis and Tx LVPECL analog supplies.
VDDA18RPA supplies the Rx PLL / Clock Recovery and Rx LVPECL analog supplies. They
are the most sensitive supplies in the device. Noise on these supplies result in deteriorated
jitter performance at the Line side. The recommendation is to have separate 1.8V supplies for
VDDA18TPA and VDDA18RPA, each one carefully filtered. The power supply noise
requirement for both VDDA18TPA and VDDA18RPA is 20 mVpp max.
LVPECL - Line Interfaces:
It is required to provide a pull-up and a pull-down resistor as close as possible to the
LINERXDATAxP and LINERXDATAxN (x = 1...4) pins on the PHAST-12N:
It is required to provide a pull-up and a pull-down resistor at the LINETXDATAxP and
LINETXDATAxN (x = 1...4) pins on the PHAST-12N:
• pull-up value (towards +3.3V) = 130
• pull-down value (towards VSS) = 82
• pull-up value (towards +3.3V) = 130
• pull-down value (towards VSS) = 82
- Selected Parameter Values -
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005