TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 177

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 7 7 o f 2 02
Offset
0x0000 0
0x0002 4 - 0
0x0004 4 - 0
0x0006 5 - 0
Bits
SerDes_LoadConfig
SysLoop
FacLoop
IndirectAccessMode
Table 52: CDR/CS Configuration
Name
- Memory Maps and Bit Descriptions -
Init
0x0 Writing 0x1 to this register will start the transmission of the con-
0x0 System Loopback Select, it routes the serialized transmit output
0x0 Facility Loopback Select, it routes the receive serial input back to
0x0 Selects the mode for the IndirectAccessData register.
trol signals to the SerDes.
When the transmission is finished this register is reset to its
default value.
Writing 0x0 to the register is ignored.
The following settings are transmitted:
•
•
•
•
•
•
•
•
•
•
•
•
to the deserializer receive input.
Each bit controls a line. The corresponding LIU is in normal oper-
ation when 0x0 and is looped back when 0x1.
•
•
•
•
•
the transmit serial output.
Each bit controls a line. The corresponding LIU is in normal oper-
ation when 0x0 and is looped back when 0x1.
•
•
•
•
•
•
•
•
CDR_CS_Setup.TxPowerDown
CDR_CS_Setup.RxPowerDown1
CDR_CS_Setup.RxPowerDown2
CDR_CS_Setup.ToplevelPowerDown
CDR_CS_Setup.OC3NotOC12
PLL_Control.TxPLL_Cap_Enable
PLL_Control.RxPLL_Cap_Enable
PLL_Control.TxPLL_PowerDown
PLL_Control.RxPLL_PowerDown
PLL_Control.CDRTune[4:0]
PLL_Control.PLLTune
All settings configured via the indirect access register
(CDR_CS_Setup.Indirect_AccessData and
Common_Config.IndirectAccessMode)
bit 0: Line 1
bit 1: Line 2
bit 2: Line 3
bit 3: Line 4
bit 4: APS
bit 0: Line 1
bit 1: Line 2
bit 2: Line 3
bit 3: Line 4
bit 4: APS
0x0: Mode0
0x8: Mode1
All others: Reserved
(T_ANALOG_Common_Config)
Description
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005