TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 38

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
MPWR
MPACK
MPINTR
MPCLK
MPA13
MPA12
MPA11
MPA10
MPA09
MPA08
MPA07
MPA06
MPA05
MPA04
MPA03
MPA02
MPA01
MPA00
Symbol
Symbol
GENERIC MOTOROLA - HOST PROCESSOR INTERFACE
Lead No. I/O/P
Lead No.
B3
L2
L1
M1
C2
D2
C1
G4
D1
B1
E4
E3
F4
B2
E2
F3
E1
F2
O(T) LVCMOS
O
I
I/O/P
I
I
LVCMOS
LVTTL Write Strobe (Active Low): This active low lead initiates a
24mA
Type
8mA
LVTTL Microprocessor Clock: This lead is the clock sourced by
LVTTL Address Bus: These leads are the address bus used by
Type
-
Lead Descriptions
write transfer between the host processor and the PHAST-12N.
Intel notation: WR
Ready: For a write access, an active edge on this lead indi-
cates that data is written to the addressed memory location.
For a read access, an active edge on this lead indicates that
the data to be read from the addressed memory location is
available on the data bus.
Active level depends on MPACKLEVEL.
Intel notation: RDY
Interrupt: This lead signals an interrupt request to the host pro-
cessor.
Active level depends on MPINTLEVEL.
the microprocessor being interfaced to this device.
Its max. frequency is 50 MHz.
Motorola notation: CLK
the host processor for accessing the PHAST-12N for a read
or write cycle.
MPA13 is the most significant bit in the location’s address.
Motorola notation: A[ ]
-
Name/Function
Name/Function
3 8 o f 2 0 2