TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 184

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
Offset
Offset
Offset
Offset
0x000A
0x000C
0x0000 0
0x0000 11 - 0
0x0000 ClockEdge_Config
0x0002 3 - 0
0x0004 Parity_Config
0x0006 0
0x0008 9 - 0
0x0000 11 - 0
0x0002 11 - 0
1
0
1
0
1
Bits
Bits
Bits
Bits
C1_LOF
ParityError
Summary
Sample_SelectNegativeClock
Edge
Output_SelectNegativeClock
Edge
ParityIncludesTiming
ParityEven
Reserved
AUG1_Mode_Config
Is_TUG_Structured
Reserved
TimingDelay
AU_PointerValue
VC3_TUG3_Mode_Config
Table 71: Telecom Bus Path Configuration
Table 70: Add Bus Common Configuration
Table 69: Add Bus Defect Summary
Table 68: Add Bus Common Defects
Name
Name
Name
Name
-
Memory Maps and Bit Descriptions
Init
0x0 Configure the edge on which the timing and data signals are sampled.
0x0 Configure the edge on which the timing signals are clocked out.
0x0 Range 0 to 15
0x1 Reserved.
0x0 Integer 0, 522
0x0 Calculate Parity over Data only, or over Data and Timing. Timing is
0x0 Even parity when 0x1, odd parity when 0x0.
Init
Init
Init
0xFFF Defect Summary, one bit per high order path. Least significant bit
0xFFF Contents of VC-3 / TUG-3, one bit per timeslot.
0x1 C1 Loss Of Frame.
0x1 Parity Error on the Telecom Bus.
0x0 Reserved.
Negative clock edge when 0x1, positive clock edge when 0x0.
Negative clock edge when 0x1, positive clock edge when 0x0.
Configure expected Delay between Timing and Data on Combus.
included when 0x1.
Sets the fixed AU pointer value used for generating Master mode
timing.
T_AUG1_Mode_Config
AUG-1 mode configuration.
T_VC3_TUG3_Mode_Config
Configuration of the VC-3/TUG-3 modes.
corresponds to the first high order path.
Each bit has following meaning (least significant bit represents the
first VC-3 / TUG-3, most significant bit the last VC-3 / TUG-3):
The corresponding VC-3 (when AU-3 is mapped in AUG-1) or TUG-3
(when AU-4 is mapped in AUG-1) contains TUG-2 when ‘1’. VC-3 /
TUG-3 contains C-3 / TU-3 respectively when ‘0’.
(t_dicb_VCx_CorrDefects_Summary)
(T_DICB_Global_CorrDefects)
(T_VC3_TUG3_Mode_Config)
(T_DICB_Common_Config)
-
(See page
Description
(See page
Description
Description
Description
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