TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 56

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
Notes:
1. The optional V1 pulse only occurs during the first frame of the low order multi-frame as indicated by the H4 byte. It is
2. The CBADCLK clock edge on which the data/parity signals are clocked in can be selected, see
3. The active CBADCLK clock edge on which the timing signals are clocked out can be selected, see
4.
CBADCLK clock period
CBADCLK duty cycle
CBADD(7-0)/CBADPAR setup time before CBADCLK
CBADD(7-0)/CBADPAR hold time after CBADCLK
CBADJ0J1/CBADSPE out valid delay from CBADCLK
always located twelve clock cycles after the corresponding J1 pulse.
page
on page
An additional delay of 0 up to 15 extra CBADCLK clock cycles can be inserted between the Add bus timing
signals, CBADJ0J1 and CBADSPE, and the Add bus data/parity,
waveforms shown correspond to a delay of 1 clock cycle.
CBADD(7-0)/
CBADJ0J1
CBADSPE
CBADCLK
CBADPAR
(Output)
(Output)
(Output)
(Input)
132. The waveforms shown correspond to the positive clock edge selection.
132. The waveforms shown correspond to the positive clock edge selection.
Figure 7. ADD Bus Timing (ADD Master Mode: Timing Signals Are Outputs)
50 pF Load
C1/J0 pulse
t
CYC
Parameter
t
PWH
-
Timing Characteristics
J1 pulse #1
t
D
Symbol
t
t
PWH
CYC
t
t
t
S
H
D
J1 pulse #2
-
J1 #1
t
S
see
Min
40
5
0
1
t
“Add Bus Delay” on page
H
J1 pulse #12
12.86
Typ
50
V1 pulse #1
“Add Bus Interface” on
“Add Bus Interface”
Max
60
6
V1 pulse #2
5 6 o f 2 0 2
%t
134. The
Unit
ns
ns
ns
ns
CYC