TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 154

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
Offset
Offset
0x000A 7 - 0
0x000C 7 - 0
0x000E 7 - 0
0x0008 7 - 0
0x0000 11 - 0
0x0004
0x0006 0
0x0008 0
13.5 INTERRUPT
Bits
Bits
RxLine1_Reset
RxLine2_Reset
RxLine3_Reset
RxLine4_Reset
APS_Interrupts_Mask
IntCtrl_Config
HINT
HINTEN
Name
Name
-
Memory Maps and Bit Descriptions
Table 6: Reset Generator
Table 7: Interrupt
Init
0x0 rw
0x0 rw
0x0 rw
0x0 rw
Init
0xFFF rw
Access
0x0 ro
0x0 rw
rw
Access
Microprocessor Controller Reset for Rx Line 1. Writing the
value 0x91 to this register generates a reset in the Receive
Line 1 clock domain.
Reset is active as long as this register contains the value 0x91.
Note: Only assert reset when RESETH = 0x91. Can be
deasserted at any time.
Microprocessor Controller Reset for Rx Line 2. Writing the
value 0x91 to this register generates a reset in the Receive
Line 2 clock domain.
Reset is active as long as this register contains the value 0x91.
Note: Only assert reset when RESETH = 0x91. Can be
deasserted at any time.
Microprocessor Controller Reset for Rx Line 3. Writing the
value 0x91 to this register generates a reset in the Receive
Line 3 clock domain.
Reset is active as long as this register contains the value 0x91.
Note: Only assert reset when RESETH = 0x91. Can be
deasserted at any time.
Microprocessor Controller Reset for Rx Line 4. Writing the
value 0x91 to this register generates a reset in the Receive
Line 4 clock domain.
Reset is active as long as this register contains the value 0x91.
Note: Only assert reset when RESETH = 0x91. Can be
deasserted at any time.
(T_INTERRUPT)
APS Interrupts Mask.
T_InterruptCtrl_Config
See APS_Interrupts register for details.
Interrupt and performance configuration.
Global device interrupt (HINT = Hardware INTerrupt).
The global device interrupt is enabled when 0x1, no
interrupt will be generated when 0x0 (HINTEN =
Hardware INTerrupt ENable).
(T_RGEN)
-
Description
Description
(See page
155)
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