MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 10

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

CAS Latency
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 below indicates the operat-
ing frequencies at which each CAS latency setting can
be used.
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
The CAS latency is the delay, in clock cycles, be-
If a READ command is registered at clock edge n,
NOTE: Each READ command may be to either bank. DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
CAS Latency = 1
T0
T0
T0
BANK,
COL n
BANK,
COL n
BANK,
COL n
READ
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
CAS Latency
T2
T2
T2
NOP
NOP
NOP
Figure 2
D
D
n + 1
OUT
OUT
n
T3
T3
T3
NOP
NOP
NOP
D
n + 2
D
D
n + 1
OUT
OUT
OUT
n
T4
T4
T4
READ
BANK,
READ
BANK,
READ
BANK,
COL b
COL b
COL b
X = 0 cycles
X = 1 cycle
D
n + 2
D
n + 3
D
n + 1
OUT
OUT
OUT
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
D
n + 3
n + 2
D
OUT
OUT
OUT
b
T6
T6
NOP
NOP
D
n + 3
D
OUT
OUT
b
DON’T CARE
T7
NOP
D
OUT
b
10
operation or incompatibility with future versions may
result.
Operating Mode
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
SPEED
- 10
Reserved states should not be used as unknown
The normal operating mode is selected by setting
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via M0-
- 8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LATENCY = 1 LATENCY = 2 LATENCY = 3
CAS
≤ 50
≤ 40
CAS Latency
ALLOWABLE OPERATING
Table 2
FREQUENCY (MHz)
MOBILE SDRAM
≤ 100
©2003 Micron Technology, Inc. All rights reserved.
CAS
≤ 83
256Mb: x16
PRELIMINARY
≤ 125
≤ 100
CAS