MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 26

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

Enter deep power-down mode.
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
DEEP POWER-DOWN
ings feature achieved by shutting off the power to the
entire memory array of the device. Data will not be
retained once Deep Power Down mode is executed.
Deep Power Down mode is entered by having all banks
idle then /CS and /WE held low with /RAS and /CAS
high at the rising edge of the clock, while CKE is low.
CKE must be held low during Deep Power Down.
be asserted high. After exiting, the following sequence
is needed in order to enter a new command. Maintain
NOP input conditions for a minimum of 200us. Issue
PRECHARGE commands for all banks. Issue eight or
more AUTOREFRESH commands. Issue a MODE REG-
ISTER set command to initialize mode register. Issue
a EXTENDED MODE REGISTER set command to ini-
tialize the extended mode register. See Figure 21A.
RAS#
CAS#
WE#
CS#
CKE
CLK
Deep Power Down mode is a maximum power sav-
In order to exit Deep Power Down mode, CKE must
Deep Power-Down
Figure 21A
Exit deep power-down mode.
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DON T CARE
26
CLOCK SUSPEND
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the in-
put pins at the time of a suspended internal clock edge
is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Fig-
ures 22 and 23.)
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
COMMAND
INTERNAL
ADDRESS
Clock Suspend During WRITE Burst
CLOCK
NOTE: For this example, burst length = 4 or greater, and DM
The clock suspend mode occurs when a column ac-
For each positive clock edge on which CKE is
CLK
CKE
Clock suspend mode is exited by registering CKE
D
IN
is LOW.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
T0
WRITE
BANK,
COL n
D
T1
n
Figure 22
IN
TRANSITIONING DATA
T2
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
T3
PRELIMINARY
NOP
n + 1
T4
D
IN
DON’T CARE
T5
n + 2
NOP
D
IN