MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 40

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

NOTES
1. All voltages referenced to V
2. This parameter is sampled; f = 1 MHz, T
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured at 0.9V with equivalent load:
10.
11. AC timing and I
12. Other input signals are allowed to transition no
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
0.9V bias, 200mV swing, V
Specified values are obtained with minimum cycle
time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range (0°C ≤ T
40°C ≤ T
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
and V
AUTO REFRESH command wake-ups should be
repeated any time the
exceeded.
cation, the clock and CKE must transit between V
and V
manner.
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to V
the input transition time is longer than 1 ns, then
the timing is referenced at V
and no longer at the V
more than once every two clocks and are otherwise
at valid V
erly initialized.
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle rate.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
DD
OH
is dependent on output loading and cycle rates.
specifications are tested after the device is prop-
or V
DD
IL
SS
Q must be powered up simultaneously. V
Q must be at same potential.) The two
(or between V
A
OL
IH
≤ +85°C for IT parts) is ensured.
. The last valid data element will meet
or V
DD
Q
IL
tests have V
levels.
IH
t
IL
REF refresh requirement is
/2 crossover point.
and V
DD
t
T = 1ns.
SS
IH
IL
= +2.5V, V
IL
t
.
t
/2 crossover point. If
WR plus
(MAX) and V
t
WR.
= 0.0V and V
CKS; clock(s) speci-
IH
30pF
) in a monotonic
A
≤ +70°C and -
DD
t
RP; clock(s)
Q = +2.5V.
J
IH
IH
= 25°C;
1.65V,
(MIN)
DD
IH
SS
40
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times dur-
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8, CL = 2 and
33. CKE is HIGH during refresh command period
34. Measured at nominal value at 70°C.
A.
B.
C. Maximum capacitance can be 3.3pF but not
D. Target values listed with alternative values in
E.
F.
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency al-
teration for the test condition.
two clocks.
ing this period.
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. V
(MIN) = -2V for a pulse width ≤ 1/3
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
t
used to reduce the data rate.
budget (
after the last WRITE is executed.
t
guaranteed by design.
t
ally a nominal value and does not result in a fail
value.
WR, and PRECHARGE commands). CKE may be
AC for -8 at CL = 3 with no load is 5.4ns and is
t
RFC (MIN) else CKE is LOW. The I
IH
CK = 10ns.
desired.
desired.
desired.
parentheses.
overshoot: V
Maximum capacitance can be 3.0 pF but not
Maximum capacitance can be 5.0pF but not
t
t
For full I/V relationships see IBIS model.
RFC must be less than or equal to
XSR must be less than or equal to
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
current will increase or decrease propor-
RP) begins 7ns after the first clock delay,
t
CK = 8ns for -8,
IH
(MAX) = V
t
CK = 10ns; for -10, CL = 3 and
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
t
CK = 10ns for -10.
256Mb: x16
DD
Q + 2V for a pulse
PRELIMINARY
IL
DD
t
undershoot: V
CK.
6 limit is actu-
t
t
RC+1CLK
RC+1CLK
IL