MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 14

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

COMMAND INHIBIT
commands from being executed by the SDRAM, re-
gardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already
in progress are not affected.
NO OPERATION (NOP)
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
and A14 should be driven LOW to prevent Extended
Mode Register.) See mode register heading in the Reg-
ister Definition section. The LOAD MODE REGISTER
command can only be issued when all banks are idle,
and a subsequent executable command cannot be is-
sued until
ACTIVE
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before open-
ing a different row in the same bank.
READ
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A8 (x16) selects the starting column location.
The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the
DQM inputs two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQM signal was regis-
tered LOW, the DQs will provide valid data.
WRITE
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
The COMMAND INHIBIT function prevents new
The NO OPERATION (NOP) command is used to
The mode register is loaded via inputs A0-A12 (A13
The ACTIVE command is used to open (or activate)
The READ command is used to initiate a burst read
The WRITE command is used to initiate a burst write
t
MRD is met.
14
inputs A0-A8 (x16) selects the starting column location.
The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of
the WRITE burst; if auto precharge is not selected, the
row will remain open for subsequent accesses. Input
data appearing on the DQs is written to the memory
array subject to the DQM input logic level appearing
coincident with the data. If a given DQM signal is regis-
tered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
PRECHARGE
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
same individual-bank PRECHARGE function de-
scribed above, without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or WRITE
command. A PRECHARGE of the bank/row that is ad-
dressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
AUTO PRECHARGE does not apply. Auto precharge is
nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this data
sheet.
AUTO REFRESH
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This
The PRECHARGE command is used to deactivate
Auto precharge is a feature which performs the
Auto precharge ensures that the precharge is initi-
AUTO REFRESH is used during normal operation of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOBILE SDRAM
t
t
RP) is completed. This is
RP) after the PRECHARGE
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
PRELIMINARY