MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 24

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 17.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
t
data element is registered. The auto precharge mode
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
WR after the clock edge at which the last desired input
COMMAND
COMMAND
Data for any WRITE burst may be truncated with a
Data for a fixed-length WRITE burst may be fol-
ADDRESS
ADDRESS
NOTE:
NOTE: Each WRITE command may be to any bank. DQM is LOW.
CLK
DQ
CLK
DQ
The WRITE command may be to any bank, and the READ command
may be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Random WRITE Cycles
WRITE
BANK,
COL n
D
T0
n
IN
BANK,
WRITE
COL n
D
T0
n
WRITE to READ
IN
n + 1
NOP
T1
D
TRANSITIONING DATA
IN
Figure 16
Figure 17
WRITE
BANK,
COL a
T1
D
TRANSITIONING DATA
a
IN
BANK,
READ
COL b
T2
WRITE
BANK,
COL x
D
T3
T2
NOP
x
IN
NOP
D
T4
WRITE
BANK,
COL m
OUT
b
T3
D
m
IN
DON’T CARE
DON’T CARE
T5
NOP
b + 1
D
OUT
24
requires a
of frequency. In addition, when truncating a WRITE
burst, the DQM signal must be used to mask input data
for the clock edge prior to, and the clock edge coinci-
dent with, the PRECHARGE command. An example is
shown in Figure 18. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
precharge can be issued coincident with the first coin-
cident clock edge (T2 in Figure 18) on an A1 Version and
with the second clock on an A2 Version (Figure 18.)
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
COMMAND
COMMAND
t WR @ t CLK ≥ 15ns
t WR = t CLK < 15ns
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
ADDRESS
ADDRESS
In the case of a fixed-length burst being executed to
DQM
DQM
CLK
DQ
DQ
BANK a,
BANK a,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WRITE
WRITE
COL n
COL n
WR of at least one clock plus time, regardless
D
D
T0
n
n
IN
IN
WRITE to PRECHARGE
n + 1
n + 1
NOP
NOP
T1
D
D
IN
IN
t
Figure 18
WR
PRECHARGE
(a or all)
BANK
T2
NOP
MOBILE SDRAM
t
WR
TRANSITIONING DATA
PRECHARGE
(a or all)
BANK
©2003 Micron Technology, Inc. All rights reserved.
T3
NOP
256Mb: x16
t RP
PRELIMINARY
NOP
NOP
T4
t
RP is met. The
t RP
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6