MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 23

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

WRITEs
as shown in Figure 13.
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
ment will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to the start address
and continue.)
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command. An ex-
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
WRITE bursts are initiated with a WRITE command,
The starting column and bank addresses are pro-
During WRITE bursts, the first valid data-in ele-
Data for any WRITE burst may be truncated with a
A9, A11: x16
A0-A8: x16
BA0,1
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
HIGH
WRITE Command
Figure 13
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
COLUMN
ADDRESS
BANK
23
ample is shown in Figure 15. Data n + 1 is either the last
of a burst of two or the last desired of a longer burst. The
256Mb SDRAM uses a pipelined architecture and there-
fore does not require the 2n rule associated with a
prefetch architecture. A WRITE command can be initi-
ated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in
Figure 16, or each subsequent WRITE may be per-
formed to a different bank.
COMMAND
ADDRESS
COMMAND
ADDRESS
CLK
DQ
NOTE: DQM is LOW. Each WRITE command may
TRANSITIONING DATA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CLK
DQ
be to any bank.
WRITE
BANK,
COL n
T0
D
WRITE to WRITE
n
IN
WRITE
WRITE Burst
BANK,
COL n
D
T0
n
IN
Figure 14
Figure 15
NOP
n + 1
T1
MOBILE SDRAM
D
IN
n + 1
NOP
T1
D
©2003 Micron Technology, Inc. All rights reserved.
IN
256Mb: x16
NOP
T2
DON’T CARE
PRELIMINARY
WRITE
BANK,
COL b
T2
D
b
IN
T3
NOP