LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 162

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysIO Usage Guide
Appendix B. sysIO Attributes Using Preference Editor User Interface
You can also assign the sysIO buffer attributes using the Pre Map Preference Editor GUI available in the ispLEVER
tools. The Pin Attribute Sheet list all the ports in your design and all the available sysIO attributes as preferences.
Clicking on each of these cells will produce a list of all the valid I/O preference for that port. Each column takes pre-
cedence over the next. Hence, when a particular IO_TYPE is chosen, the DRIVE, PULLMODE and SLEWRATE
columns will only list the valid combinations for that IO_TYPE. The user can lock the pin locations using the pin
location column of the Pin Attribute sheet. Right-clicking on a cell will list all the available pin locations. The Prefer-
ence Editor will also conduct a DRC check to look for incorrect pin assignments.
You can enter the DIN/ DOUT preferences using the Cell Attributes Sheet of the Preference Editor. All the prefer-
ences assigned using the Preference Editor are written into the logical preference file (.lpf).
Figure 8-4 and Figure 8-5 show the Pin Attribute Sheet and the Cell Attribute Sheet views of the Preference Editor.
For further information on how to use the Preference Editor, refer to the ispLEVER Help documentation located in
the Help menu option of the software.
Figure 8-4. Pin Attributes Tab
Figure 8-5. Cell Attributes Tab
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